The present invention relates to flash memory devices and, more particularly, to a flash memory device which performs address control based on bad block information.
In flash memory devices, a bad block refers to a block that cannot be repaired even through column repair. Bad blocks should be generally 2% or less of all of the blocks in a data page.
A determination is made whether a block is bad at the time of a wafer test during the manufacturing process of a flash memory device. A memory block, which is determined to be a bad block, is disabled in hardware by cutting a block fuse in a path that enables a corresponding block.
The block fuse functions to make impossible the enabling of a word line of the block, thereby disabling the operation of a corresponding block.
FIG. 1 is a circuit diagram of a block select circuit employing a conventional block fuse. This drawing shows a partial block select circuit that outputs a block enable signal. Referring to FIG. 1, the block select circuit includes first and second PMOS transistors P1, P2, first and second NAND gates NA1, NA2, and a fuse F.
The first and second PMOS transistors P1, P2 are connected in series between a power supply voltage node and a node a1. The gates of the first and second PMOS transistors P1, P2 are commonly connected to a ground node. Thus, the first and second PMOS transistors P1, P2 are always turned on.
The first NAND gate NA1 outputs input block addresses XA, XB, XC and XD to the node a1. The block addresses XA, XB, XC and XD are decoded by employing a row address input together with a program or read operation command of a flash memory device.
A fuse F is connected between the first NAND gate NA1 and the node a1.
The output of the first NAND gate NA1 is decided by the block addresses XA, XB, XC and XD. When the block addresses XA, XB, XC and XD are a high level, the first NAND gate NA1 outputs a low-level signal, thereby making the node a1 have a low level. When a control signal PGMPREb of a low level is input, the second NAND gate NA2 outputs a low-level signal, and the enable signal is input to a block corresponding to the block addresses XA, XB, XC and XD.
This block select circuit is connected to every block. The enable signal is not input to a block that is a bad block by cutting the fuse F.
A bad block refers to a memory block having failed memory cells that cannot be corrected through column repair. In flash memory devices, the percentage of bad blocks generally falls within 2%. A determination of whether a block is bad is performed during a wafer test of a flash memory device.
In order to disable the bad block, fuses are necessary in all of the memory blocks. Accordingly, the area occupied by the fuses is large.